EP1810GM883 vs EP1810GI-45 对比

详细并排对比 EP1810GM883 出自 Altera 和 EP1810GI-45 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1810GM883 EP1810GI-45
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $175.00 $56.40
Family Classic EPLD (EP1810 series) Altera Classic EPLD
Device Type UV-Erasable Programmable Logic Device (EPLD) UV Erasable Programmable Logic Device (EPLD)
Macrocells 48 24
Dedicated Inputs 12 —
User I/O Pins 48 —
Total Terminals 68 —
Global Clocks 4 —
Supply Voltage (Vcc) 4.5 V to 5.5 V (nominal 5 V) —
Propagation Delay (tpd) 45 ns (max) 45 ns
Maximum Toggle Frequency (fmax) [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] —
Process Technology CMOS, UV-erasable —
封装 68-Pin Ceramic Pin Grid Array (PGA) —
工作温度 -55C to +125C (MIL-STD-883 Class B) [DATA_NEEDED: operating temperature range]
Screening MIL-STD-883 Class B (suffix '883' denotes MIL processing) —
安装类型 Through-Hole (PGA socket) Through-Hole
RoHS 状态 [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] Non-compliant (ceramic PGA)
Lead-Free [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] No
Flip-Flops — 48
Speed Grade — -45
Technology — CMOS
Package Type — Ceramic Pin Grid Array with UV window
引脚数量 — 68
Programmable — Yes (UV-erasable, electrically programmable)
电源电压 — [DATA_NEEDED: VCC range]

数据手册与资源

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