EP1810GM883B vs EP1810LC-20T 对比

详细并排对比 EP1810GM883B 出自 Altera 和 EP1810LC-20T 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1810GM883B EP1810LC-20T
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $125.40 $9.95
Device Family EP1810 (Classic EPLD) —
Macrocells 48 48
User Flip-Flops Up to 64 —
Total Inputs 60 —
Dedicated Inputs 12 —
I/O Pins 48 (bidirectional, tri-state) —
Propagation Delay (tPD) 50 ns max —
Supply Voltage (VCC) 4.5 V to 5.5 V 5 V
Technology CMOS, UV-erasable —
工作温度 -55 °C to +125 °C (Military, MIL-STD-883B) 0C to +70C (commercial)
Package Type Ceramic Pin Grid Array (PGA), 84 pins PLCC-68 (J-lead)
Package Designator GM (ceramic PGA) —
Processing Level MIL-STD-883B (Class B) —
Programming Method UV-erasable / Altera programming hardware —
安装类型 Through-hole (PGA socket or PCB through-hole) Surface Mount (socket-compatible)
Lead-Free / RoHS [DATA_NEEDED: lead-free status] —
Logic Family TTL-compatible I/O —
Family — Altera Classic EPLD
Product Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 900 gates
Logic Array Blocks (LABs) — 4 x 12 macrocells
Maximum Toggle Frequency — 50 MHz
Pin-to-Pin Logic Delay (tPD) — 20 ns
Configuration Memory — On-chip EEPROM (non-volatile)
Programming Interface — JTAG (IEEE 1149.1) and Altera Master/Slave serial
Shipping Format — Tape & Reel ("T" suffix)
RoHS 状态 — Non-compliant (legacy 5V PLCC)

数据手册与资源

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