EP1810JI-35 vs EP1810GM883B 对比
详细并排对比 EP1810JI-35 出自 Intel 和 EP1810GM883B 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810JI-35 | EP1810GM883B |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $18.60 | $125.40 |
| Device Family | Classic EPLD | EP1810 (Classic EPLD) |
| Macrocells | 48 | 48 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | 12 |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| 封装 | 28-pin JLCC (J-leaded ceramic, windowed) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| 工作温度 | -40C to +85C (Industrial) | -55 °C to +125 °C (Military, MIL-STD-883B) |
| 电源电压 | 5 V (typical classic EPLD) | — |
| Programmability | UV-erase, windowed for lab reprogram | — |
| 安装类型 | Through-Hole (J-lead) | Through-hole (PGA socket or PCB through-hole) |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | — |
| MSL 等级 | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| User Flip-Flops | — | Up to 64 |
| Total Inputs | — | 60 |
| I/O Pins | — | 48 (bidirectional, tri-state) |
| Propagation Delay (tPD) | — | 50 ns max |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Technology | — | CMOS, UV-erasable |
| Package Type | — | Ceramic Pin Grid Array (PGA), 84 pins |
| Package Designator | — | GM (ceramic PGA) |
| Processing Level | — | MIL-STD-883B (Class B) |
| Programming Method | — | UV-erasable / Altera programming hardware |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Logic Family | — | TTL-compatible I/O |