EP1810LC-45 vs EP1810LC-25 对比
详细并排对比 EP1810LC-45 出自 Rochester Electronics 和 EP1810LC-25 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete
规格对比
| 参数 | EP1810LC-45 | EP1810LC-25 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $49.90 | $8.40 |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 900 | — |
| Macro Cells | 48 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Logic Array Blocks | 4 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Maximum Operating Frequency | 22.2 MHz | — |
| Supply Voltage (Vcc) | 5 V (±5%) | — |
| Process Technology | 5 V CMOS EPROM | — |
| 封装 | 68-pin PLCC (J-lead) | 68-pin JLCC (J-leaded ceramic chip carrier) |
| 工作温度 | 0 °C to +70 °C (commercial) | [DATA_NEEDED: temperature grade for LC package] |
| 安装类型 | Surface Mount (PLCC socket compatible) | Surface Mount |
| RoHS 状态 | [DATA_NEEDED: RoHS status of Rochester-sourced part] | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| Macrocells | — | 48 |
| Propagation Delay (tPD) | — | 25 ns |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 5 V (TTL-compatible) |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| Package Code | — | LC = 68-pin JLCC |
| Technology | — | CMOS EPLD (erasable programmable logic device) |
| Programmable Interconnect | — | Global + Local buses |
| Programming Method | — | Altera Classic programmer + MAX+PLUS II legacy flow |
| 生命周期状态 | — | Obsolete (legacy Altera Classic family) |