EP1810LC-45 vs EP1810LC-25 Comparaison
Comparaison détaillée côte à côte de EP1810LC-45 par Rochester Electronics et EP1810LC-25 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete
Comparaison des spécifications
| Paramètre | EP1810LC-45 | EP1810LC-25 |
|---|---|---|
| Marque | Rochester Electronics | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $49,90 | $8,40 |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 900 | — |
| Macro Cells | 48 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Logic Array Blocks | 4 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Maximum Operating Frequency | 22.2 MHz | — |
| Supply Voltage (Vcc) | 5 V (±5%) | — |
| Process Technology | 5 V CMOS EPROM | — |
| Boîtier | 68-pin PLCC (J-lead) | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Température de fonctionnement | 0 °C to +70 °C (commercial) | [DATA_NEEDED: temperature grade for LC package] |
| Type de montage | Surface Mount (PLCC socket compatible) | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status of Rochester-sourced part] | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| Macrocells | — | 48 |
| Propagation Delay (tPD) | — | 25 ns |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 5 V (TTL-compatible) |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| Package Code | — | LC = 68-pin JLCC |
| Technology | — | CMOS EPLD (erasable programmable logic device) |
| Programmable Interconnect | — | Global + Local buses |
| Programming Method | — | Altera Classic programmer + MAX+PLUS II legacy flow |
| Statut du cycle de vie | — | Obsolete (legacy Altera Classic family) |