EP1810LI-35 vs EP1810LI-45 对比

详细并排对比 EP1810LI-35 出自 Altera 和 EP1810LI-45 出自 Rochester Electronics。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1810LI-35 EP1810LI-45
品牌 Altera Rochester Electronics
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 有效
库存状态 有库存 有库存
单价(USD) $78.05 $64.10
Manufacturer Rochester Electronics, LLC (original Altera design) Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line)
Part Family Altera Classic EPLD —
Device Type Erasable Programmable Logic Device (EPLD) —
Macrocells 48 48
Propagation Delay (tPD) 35 ns —
Speed Grade 35 (slowest in EP1810L family) —
封装 68-pin PLCC (J-Lead, plastic) 68-pin PLCC / PQCC68 (J-Lead)
Pin/Package Code PLCC-68 / PQCC68 —
Technology CMOS, UV-erasable EPROM configuration cell CMOS, UV-erasable EPROM configuration
电源电压 5 V (TTL-compatible I/O) 5 V
工作温度 -40 C to +85 C (industrial, 'I' suffix) —
安装类型 Surface Mount (PLCC socket compatible) —
JTAG Boundary Scan IEEE 1149.1 compliant —
Logic Elements Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
MSL 等级 [DATA_NEEDED: MSL rating] —
Product Type — EPLD (Erasable Programmable Logic Device)
Family — Altera Classic
Usable Gates — 900
Maximum User I/O — 64 inputs / 48 outputs
Pin-to-Pin Logic Delay (tPD) — 45 ns
Counter Frequency (fCNT) — up to 100 MHz
Setup Time (tSU) — [DATA_NEEDED: setup time]
工作温度范围 — -40 C to +85 C (Industrial, 'I' suffix)
Logic Blocks — 12 LABs of 4 macrocells each
Configuration Memory — Non-volatile UV-erasable EPROM
Programming Method — Altera programming hardware with MAX+PLUS II / legacy tools

数据手册与资源

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