EP1810LI-35 vs EP1810LI-45 비교

다음의 상세 나란히 비교: EP1810LI-35 제조: Altera 및 EP1810LI-45 제조: Rochester Electronics. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP1810LI-35 EP1810LI-45
브랜드 Altera Rochester Electronics
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete 활성
재고 상태 In Stock In Stock
단가 (USD) $78.05 $64.10
Manufacturer Rochester Electronics, LLC (original Altera design) Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line)
Part Family Altera Classic EPLD —
Device Type Erasable Programmable Logic Device (EPLD) —
Macrocells 48 48
Propagation Delay (tPD) 35 ns —
Speed Grade 35 (slowest in EP1810L family) —
패키지 68-pin PLCC (J-Lead, plastic) 68-pin PLCC / PQCC68 (J-Lead)
Pin/Package Code PLCC-68 / PQCC68 —
Technology CMOS, UV-erasable EPROM configuration cell CMOS, UV-erasable EPROM configuration
공급 전압 5 V (TTL-compatible I/O) 5 V
동작 온도 -40 C to +85 C (industrial, 'I' suffix) —
실장 유형 Surface Mount (PLCC socket compatible) —
JTAG Boundary Scan IEEE 1149.1 compliant —
Logic Elements Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) —
RoHS 상태 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
MSL 레벨 [DATA_NEEDED: MSL rating] —
Product Type — EPLD (Erasable Programmable Logic Device)
Family — Altera Classic
Usable Gates — 900
Maximum User I/O — 64 inputs / 48 outputs
Pin-to-Pin Logic Delay (tPD) — 45 ns
Counter Frequency (fCNT) — up to 100 MHz
Setup Time (tSU) — [DATA_NEEDED: setup time]
동작 온도 범위 — -40 C to +85 C (Industrial, 'I' suffix)
Logic Blocks — 12 LABs of 4 macrocells each
Configuration Memory — Non-volatile UV-erasable EPROM
Programming Method — Altera programming hardware with MAX+PLUS II / legacy tools

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