EP1810LI-45 vs EP1810LI-35 对比

详细并排对比 EP1810LI-45 出自 Rochester Electronics 和 EP1810LI-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1810LI-45 EP1810LI-35
品牌 Rochester Electronics Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $64.10 $78.05
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic —
Usable Gates 900 —
Macrocells 48 48
Maximum User I/O 64 inputs / 48 outputs —
Pin-to-Pin Logic Delay (tPD) 45 ns —
Counter Frequency (fCNT) up to 100 MHz —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Technology CMOS, UV-erasable EPROM configuration CMOS, UV-erasable EPROM configuration cell
电源电压 5 V 5 V (TTL-compatible I/O)
工作温度范围 -40 C to +85 C (Industrial, 'I' suffix) —
封装 68-pin PLCC / PQCC68 (J-Lead) 68-pin PLCC (J-Lead, plastic)
Logic Blocks 12 LABs of 4 macrocells each —
Configuration Memory Non-volatile UV-erasable EPROM —
Programming Method Altera programming hardware with MAX+PLUS II / legacy tools —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Manufacturer Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) Rochester Electronics, LLC (original Altera design)
Part Family — Altera Classic EPLD
Device Type — Erasable Programmable Logic Device (EPLD)
Propagation Delay (tPD) — 35 ns
Speed Grade — 35 (slowest in EP1810L family)
Pin/Package Code — PLCC-68 / PQCC68
工作温度 — -40 C to +85 C (industrial, 'I' suffix)
安装类型 — Surface Mount (PLCC socket compatible)
JTAG Boundary Scan — IEEE 1149.1 compliant
Logic Elements — Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA)
Lead-Free — [DATA_NEEDED: lead-free status]
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

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