EP1K100QC208-3 vs EP1K100QI208-2 对比

详细并排对比 EP1K100QC208-3 出自 Altera 和 EP1K100QI208-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1K100QC208-3 EP1K100QI208-2
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $60.04 $23.90
Product Family ACEX 1K —
Device Type FPGA (Field Programmable Gate Array) —
Process Technology 0.22 um CMOS 0.22 umm CMOS SRAM
Typical Gate Count 100,000 gates —
Number of Logic Elements 4,992 —
Logic Array Blocks (LABs) 624 624
Total RAM Bits 49,152 bits —
Maximum User I/O 147 —
Maximum Internal Clock Frequency 200 MHz —
Core Supply Voltage 2.5 V —
Package Type 208-Pin BFQFP (PQFP) —
Number of Terminals 208 —
Terminal Form Gull Wing —
Package Shape Square —
Temperature Grade Commercial —
安装类型 Surface Mount Surface Mount
Speed Grade -3 —
RoHS / Lead-Free Suffix No -N suffix; compliance not verified in retrieved source data —
I/O Standards Supported [DATA_NEEDED: supported I/O standards] LVTTL, LVCMOS, PCI, 5V tolerant
Configuration Memory SRAM-based loadable PLD —
Family — ACEX-1K
Logic Elements — 4,992 cells
System Gates — 100,000
Embedded Memory (EAB) — 49,152 bits
User I/Os — 147
Maximum Operating Frequency — 250 MHz
Core Voltage (VCCINT) — 2.5 V
封装 — 208-pin PQFP (BFQFP)
Pitch — 0.5 mm
工作温度 — -40C to +85C (Industrial)
Configuration Interface — JTAG (IEEE 1149.1) / serial / EPC2
Global Clock Networks — 4
RoHS 状态 — [DATA_NEEDED: RoHS compliance status]

数据手册与资源

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