EP1K10TC100-3N vs EP1K10TC100-2 对比
详细并排对比 EP1K10TC100-3N 出自 Intel 和 EP1K10TC100-2 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EP1K10TC100-3N - 10K-Gate ACEX-1K FPGA, 576 Cells, 66 I/O, 100-TQFP | Intel / Altera
EP1K10TC100-3N Obsolete规格对比
| 参数 | EP1K10TC100-3N | EP1K10TC100-2 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $19.95 | $9.85 |
| Series | ACEX-1K | — |
| Family | ACEX 1K | ACEX-1K |
| Manufacturer | Intel (formerly Altera) | — |
| Typical Gate Count | 10,000 gates | — |
| Logic Elements (Cells) | 576 | — |
| Embedded Memory (EAB) | 12,288 bits | — |
| Number of LABs | 72 | — |
| User I/O Count | 66 | — |
| Operating Voltage (Core) | 2.5 V | — |
| Process Technology | 0.22 µm CMOS | 0.22 μm CMOS |
| Maximum Internal Clock Frequency | 200 MHz | — |
| Speed Grade | -3 (commercial) | — |
| 封装 | 100-pin TQFP | 100-pin TQFP (TQFP-100) |
| JTAG Support | Yes (IEEE 1149.1-1990) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 (5.0 V) | — |
| Configuration | JTAG / serial configuration device | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | 0 °C to 70 °C (TA, commercial) |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | Compliant (per Heisener / DigiKey listings) |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Elements / Cells | — | 576 |
| Number of Logic Array Blocks (LABs/CLBs) | — | 72 |
| Total RAM Bits | — | 12288 |
| Number of Gates | — | 10000 (typical); 56000 (maximum) |
| Number of User I/O | — | 66 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Pin-to-Pin Logic Delay | — | 0.5 ns |
| Maximum Internal Frequency | — | 200 MHz (per FPGAkey listing) |
| Core Supply Voltage (VCCINT) | — | 2.375 V to 2.625 V (2.5 V nominal) |
| I/O Supply Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO range] |
| 安装类型 | — | Surface Mount |
| Configuration Method | — | SRAM, serial / JTAG (IEEE 1149.1) |
| Lead-Free | — | Yes |