EP1S10F484C7N vs EP1S10F484C5N 对比
详细并排对比 EP1S10F484C7N 出自 Intel 和 EP1S10F484C5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1S10F484C7N | EP1S10F484C5N |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $162.00 | $52.00 |
| Family | Stratix (EP1S) | Stratix (original) |
| Manufacturer | Intel (formerly Altera) | — |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Core Voltage | 1.5 V | — |
| Logic Elements | 10,570 | — |
| Logic Array Blocks (LABs) | 1,057 | 1,057 |
| Embedded Memory (Total) | 920,448 bits | — |
| Embedded Memory Blocks | TriMatrix (M512/M4K/M-RAM) | — |
| Embedded DSP Blocks | 48 | 6 (≈48 9-bit multipliers) |
| Maximum User I/O | 335 | 335 |
| PLLs | 12 | 4 |
| 封装 | 484-ball FineLine BGA (FBGA-484), 23 x 23 mm, 1 mm pitch | 484-ball FCBGA (F484), 23 x 23 mm, 1.0 mm pitch |
| Speed Grade | C7 (-7) | — |
| Operating Temperature (Commercial) | 0 C to +85 C | — |
| Configuration Methods | JTAG, Passive Serial, Passive Parallel | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | — |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| Series | — | Stratix |
| Logic Elements (LEs) | — | 10,570 |
| Embedded Memory Bits | — | 920,448 |
| TriMatrix Memory Blocks | — | 14 |
| Global Clock Networks | — | 12 |
| User I/O Standard Support | — | LVDS, LVPECL, PCI-X, RapidIO, DDR |
| Core Voltage (VCCINT) | — | 1.5 V |
| Maximum Internal Frequency | — | 500 MHz (per Stratix datasheet) |
| Operating Temperature (TJ) | — | 0 °C to 85 °C (Commercial) |
| 安装类型 | — | Surface Mount |
| Configuration Method | — | JTAG / Passive Serial / Active Serial |
| Device Status | — | Obsolete - last time buy completed |
| Design Toolchain | — | Quartus II (≤ v13.0) |