EP1S20F484C6N vs EP1S10F484C5N 对比

详细并排对比 EP1S20F484C6N 出自 Intel 和 EP1S10F484C5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1S20F484C6N EP1S10F484C5N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $440.00 $52.00
Family Stratix Stratix (original)
Logic Elements 18,460 —
Embedded Memory 1,669,248 bits —
DSP Blocks [DATA_NEEDED: DSP block count] —
User I/O Pins 361 —
封装 484-Ball FCBGA (23 x 23 mm, 1.0 mm pitch) 484-ball FCBGA (F484), 23 x 23 mm, 1.0 mm pitch
Process Technology 130 nm CMOS 0.13 µm CMOS
Core Supply Voltage 1.5 V —
I/O Supply Voltage [DATA_NEEDED: I/O voltage - check datasheet] —
工作温度 0 C to 85 C (Commercial) —
Speed Grade 6 —
Maximum Internal Clock 450.05 MHz —
Configuration Interface JTAG (IEEE 1149.1), Serial/Parallel (AS/PS) - EPC device compatible —
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: confirm via Intel product page] —
Lead-Free [DATA_NEEDED: confirm] —
Series — Stratix
Logic Elements (LEs) — 10,570
Logic Array Blocks (LABs) — 1,057
Embedded Memory Bits — 920,448
TriMatrix Memory Blocks — 14
Embedded DSP Blocks — 6 (≈48 9-bit multipliers)
PLLs — 4
Global Clock Networks — 12
Maximum User I/O — 335
User I/O Standard Support — LVDS, LVPECL, PCI-X, RapidIO, DDR
Core Voltage (VCCINT) — 1.5 V
Maximum Internal Frequency — 500 MHz (per Stratix datasheet)
Operating Temperature (TJ) — 0 °C to 85 °C (Commercial)
Configuration Method — JTAG / Passive Serial / Active Serial
Device Status — Obsolete - last time buy completed
Design Toolchain — Quartus II (≤ v13.0)

数据手册与资源

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