EP1S20F672C7 vs EP1S20B672C7N 对比
详细并排对比 EP1S20F672C7 出自 Intel 和 EP1S20B672C7N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1S20F672C7 | EP1S20B672C7N |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $195.00 | $320.00 |
| Series | Stratix | Stratix |
| Family | Altera Stratix FPGA | Stratix (original) |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Embedded Memory Bits | 1,669,248 | 1,669,248 bits |
| User I/O Pins | 426 | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| 封装 | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) | — |
| Logic Family | CMOS, SRAM-based | CMOS |
| Core Supply Voltage | 1.5 V | — |
| 工作温度 | 0C to 85C (commercial) | 0 °C to 85 °C (Commercial Extended) |
| Speed Grade | C7 | -7 |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel, Active Serial | — |
| 安装类型 | Surface Mount | Surface Mount (BGA) |
| MSL 等级 | [DATA_NEEDED: MSL level] | 3 (per JEDEC J-STD-020) |
| RoHS 状态 | unknown | [DATA_NEEDED: RoHS compliance] |
| Clock PLLs | Up to 10 | — |
| Process Technology | — | 0.13 µm CMOS |
| LABs / CLBs | — | 1,846 |
| Maximum User I/O | — | 426 |
| Number of Pins / Balls | — | 672 |
| Package Type | — | 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) |
| Supply Voltage (Core, VCCINT) | — | 1.5 V |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |