EP1S60B956C6 vs EP1S30B956C6 对比

详细并排对比 EP1S60B956C6 出自 Altera 和 EP1S30B956C6 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1S60B956C6 EP1S30B956C6
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $339.20 $78.00
Series Stratix (EP1S) —
Logic Elements 57,120 —
Total RAM Bits 5,215,104 —
Number of LABs/CLBs 5712 —
Number of I/O 683 —
封装 956-BBGA, FCBGA (40 x 40 mm) 956-ball FCBGA (BGA-956), 40 x 40 mm, 1.27 mm pitch
Supplier Device Package 956-BGA (40x40) —
安装类型 Surface Mount (BGA) Surface Mount
工作温度 0 C to +85 C (Commercial) 0 C to 85 C (Commercial)
Core Voltage - Supply 1.425 V to 1.575 V —
Voltage - Supply 1.425 V to 1.575 V —
引脚数 956 —
Form of Terminal Ball (BGA) —
Package Code BGA / FCBGA —
RoHS 状态 [DATA_NEEDED: RoHS status] Not confirmed - pre-RoHS part
Family — Stratix
Logic Elements (LEs) — 32,470
Logic Array Blocks (LABs) — 3,247
Embedded Memory Bits — 3,317,184 (approximately 3.4 Mbit)
Maximum User I/O — 683
Process Technology — 130 nm CMOS
Core Voltage (VCCINT) — 1.5 V
Speed Grade — C6
Maximum Internal Frequency — 450.05 MHz (per family datasheet)
DSP Blocks — Yes (Stratix DSP blocks)
PLLs — Up to 12
Configuration Modes — Passive Serial (PS), Passive Parallel (PP), JTAG
MSL 等级 — [DATA_NEEDED: MSL level]
Lead-Free — Unknown

数据手册与资源

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