EP1S60F1020C6N vs EP1S60F1020C7 对比

详细并排对比 EP1S60F1020C6N 出自 Intel 和 EP1S60F1020C7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1S60F1020C6N EP1S60F1020C7
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $195.00 $1,750.00
Series Stratix Stratix
Family Stratix (EP1S) Stratix (EP1S60)
Logic Elements (LEs) 57,120 —
Logic Cells 6,570 blocks (per chipdig datasheet summary) —
Embedded RAM (Total Bits) 5,215,104 bits —
Embedded Multipliers 773 (18x18) —
Maximum User I/O Pins Per datasheet, package-dependent (F1020 variant) —
Package Type 1020-ball FBGA (FineLine BGA), 33 x 33 mm, 1 mm pitch —
Logic Family / Process CMOS, 0.13 µm —
工作温度 0°C to +85°C (Commercial) 0C to +85C (Commercial)
电源电压 Per datasheet (Stratix Device Handbook Vol. 1) —
Speed Grade C6 (mid-tier) 7
Lead-Free / Pb-Free Yes (suffix 'N') —
RoHS 状态 Compliant (per 'N' suffix) Compliant (lead-free)
安装类型 Surface Mount (BGA) Surface Mount
MSL 等级 [DATA_NEEDED: MSL rating] 3 (per BGA moisture-sensitivity norms)
Configuration JTAG / Passive Serial / Fast Passive Parallel via MSEL pins —
PLL Count 12 (per Stratix family datasheet) —
Memory Block Types TriMatrix (M512, M4K, M-RAM) —
Logic Elements — 57,120
Total Memory Bits — 5,215,104
Maximum User I/O — 773
封装 — 1020-BBGA, FCBGA, 33 x 33 mm, 1.0 mm pitch
Logic Family — CMOS
Core Supply Voltage — 1.5 V
Logic Cells / Logic Blocks — 6,570 (per datasheet Section I nomenclature)
DSP Blocks — Embedded dedicated multiplier / adder blocks
PLLs — Up to 12 enhanced PLLs per die
Configuration Method — Serial or parallel with optional decompression

数据手册与资源

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