EP1S60F1020C7 vs EP1SGX40FF1020C7 对比
详细并排对比 EP1S60F1020C7 出自 Altera 和 EP1SGX40FF1020C7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1S60F1020C7 | EP1SGX40FF1020C7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $1,750.00 | $750.00 |
| Series | Stratix | Stratix GX |
| Family | Stratix (EP1S60) | Stratix GX (EP1SGX40) |
| Logic Elements | 57,120 | — |
| Total Memory Bits | 5,215,104 | — |
| Maximum User I/O | 773 | — |
| 封装 | 1020-BBGA, FCBGA, 33 x 33 mm, 1.0 mm pitch | 1020-ball FC-FBGA (S-PBGA-B1020) |
| 安装类型 | Surface Mount | Surface Mount |
| Logic Family | CMOS | — |
| 工作温度 | 0C to +85C (Commercial) | 0 °C to 85 °C (commercial) |
| Core Supply Voltage | 1.5 V | — |
| Speed Grade | 7 | 7 (-7, mid-speed) |
| Logic Cells / Logic Blocks | 6,570 (per datasheet Section I nomenclature) | — |
| DSP Blocks | Embedded dedicated multiplier / adder blocks | — |
| PLLs | Up to 12 enhanced PLLs per die | 8 enhanced + per-transceiver PLLs |
| Configuration Method | Serial or parallel with optional decompression | — |
| MSL 等级 | 3 (per BGA moisture-sensitivity norms) | — |
| RoHS 状态 | Compliant (lead-free) | Compliant |
| Logic Elements (LE) | — | 41,250 |
| Configurable Logic Blocks (CLB) | — | 4,125 |
| Embedded Memory (bits) | — | 3,423,744 |
| User I/O Pins | — | 624 |
| Number of Logic Array Blocks (LAB) | — | 4,125 |
| Number of I/O Banks | — | 12 |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Process Technology | — | CMOS |
| Package Dimensions | — | 33 mm × 33 mm |
| Ball Pitch | — | 1.00 mm |
| Configuration Modes | — | PS, PPS, PPA, JTAG, AS |
| DSP Blocks (9-bit) | — | 176 |
| Transceiver Channels | — | 20 full-duplex 3.1875 Gbps + 14 dedicated full-duplex 1.25 Gbps |