EP1SGX25DF672C6 vs EP1SGX25DF67216 对比

详细并排对比 EP1SGX25DF672C6 出自 Intel 和 EP1SGX25DF67216 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1SGX25DF672C6 EP1SGX25DF67216
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $96.50 $198.00
Series Stratix GX —
Logic Elements 25,660 LE 25,660
Number of LABs 2,566 —
Total RAM Bits 1,944,576 bits 1,944,576
User I/O Count 455 —
Number of Transceivers 6 channels (per Stratix GX family) —
Max Transceiver Data Rate 3.125 Gbps 3.1875 Gbps per channel
Core Voltage 1.5 V —
工作温度 0C to +85C (commercial) Industrial, -40C to +100C (I-suffix family)
封装 672-BBGA FineLine BGA 672-ball FineLine BGA (DF672)
Package Dimensions 33 x 33 mm —
Ball Pitch 1.0 mm —
安装类型 Surface Mount Surface Mount (BGA)
Lead-Free / RoHS Lead-Free (per FBGA suffix family) —
Process Technology CMOS —
Family — Stratix GX
Embedded Multipliers (18x18) — [DATA_NEEDED: 18x18 multiplier count]
Number of PLLs — 4
Number of Transceiver Channels — 8 (4 in each of 2 banks)
Min Transceiver Data Rate — 500 Mbps
Core Supply Voltage — 1.5 V
Auxiliary Supply Voltage — 3.3 V
I/O Supply Voltage — 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank)
Maximum User I/O Pins — [DATA_NEEDED: user I/O count for DF672 package]
On-Die Termination — Yes, 100-ohm differential
Pre-emphasis / Equalization — Programmable (transmitter pre-emphasis; receiver adaptive equalization)
Configuration Schemes — Passive serial, fast passive parallel, JTAG, Altera enhanced configuration
RoHS 状态 — Lead-free / RoHS compliant (per Altera product family documentation)

数据手册与资源

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