EP1SGX25DF672I6 vs EP1SGX25DF67216 对比

详细并排对比 EP1SGX25DF672I6 出自 Intel 和 EP1SGX25DF67216 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1SGX25DF672I6 EP1SGX25DF67216
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $145.00 $198.00
Series Stratix GX —
Family Stratix GX Stratix GX
Logic Elements 25,660 25,660
Total RAM Bits 1,944,576 1,944,576
User I/O Count 455 —
封装 672-BBGA (FC-FBGA), 33 x 33 mm, 1.0 mm pitch 672-ball FineLine BGA (DF672)
Process Technology 130 nm CMOS —
Core Supply Voltage (VCCINT) 1.5 V —
工作温度 -40C to +85C (industrial, I6 grade) Industrial, -40C to +100C (I-suffix family)
Temperature Grade Industrial (I6) —
Maximum Internal Frequency 5000 MHz (per datasheet header) —
安装类型 Surface Mount Surface Mount (BGA)
Lead Free / RoHS Yes / Compliant —
引脚数 672 —
DSP Blocks Yes (embedded multipliers) —
On-chip Transceivers Yes (Stratix GX embedded MGTs) —
Clock Management PLLs (on-chip) —
Logic Family / Base Technology CMOS —
Embedded Multipliers (18x18) — [DATA_NEEDED: 18x18 multiplier count]
Number of PLLs — 4
Number of Transceiver Channels — 8 (4 in each of 2 banks)
Max Transceiver Data Rate — 3.1875 Gbps per channel
Min Transceiver Data Rate — 500 Mbps
Core Supply Voltage — 1.5 V
Auxiliary Supply Voltage — 3.3 V
I/O Supply Voltage — 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank)
Maximum User I/O Pins — [DATA_NEEDED: user I/O count for DF672 package]
On-Die Termination — Yes, 100-ohm differential
Pre-emphasis / Equalization — Programmable (transmitter pre-emphasis; receiver adaptive equalization)
Configuration Schemes — Passive serial, fast passive parallel, JTAG, Altera enhanced configuration
RoHS 状态 — Lead-free / RoHS compliant (per Altera product family documentation)

数据手册与资源

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