EP1SGX25DF672I6 vs EP1SGX25DF67216 비교

다음의 상세 나란히 비교: EP1SGX25DF672I6 제조: Intel 및 EP1SGX25DF67216 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP1SGX25DF672I6 EP1SGX25DF67216
브랜드 Intel Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $145.00 $198.00
Series Stratix GX —
Family Stratix GX Stratix GX
Logic Elements 25,660 25,660
Total RAM Bits 1,944,576 1,944,576
User I/O Count 455 —
패키지 672-BBGA (FC-FBGA), 33 x 33 mm, 1.0 mm pitch 672-ball FineLine BGA (DF672)
Process Technology 130 nm CMOS —
Core Supply Voltage (VCCINT) 1.5 V —
동작 온도 -40C to +85C (industrial, I6 grade) Industrial, -40C to +100C (I-suffix family)
Temperature Grade Industrial (I6) —
Maximum Internal Frequency 5000 MHz (per datasheet header) —
실장 유형 Surface Mount Surface Mount (BGA)
Lead Free / RoHS Yes / Compliant —
핀 수 672 —
DSP Blocks Yes (embedded multipliers) —
On-chip Transceivers Yes (Stratix GX embedded MGTs) —
Clock Management PLLs (on-chip) —
Logic Family / Base Technology CMOS —
Embedded Multipliers (18x18) — [DATA_NEEDED: 18x18 multiplier count]
Number of PLLs — 4
Number of Transceiver Channels — 8 (4 in each of 2 banks)
Max Transceiver Data Rate — 3.1875 Gbps per channel
Min Transceiver Data Rate — 500 Mbps
Core Supply Voltage — 1.5 V
Auxiliary Supply Voltage — 3.3 V
I/O Supply Voltage — 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank)
Maximum User I/O Pins — [DATA_NEEDED: user I/O count for DF672 package]
On-Die Termination — Yes, 100-ohm differential
Pre-emphasis / Equalization — Programmable (transmitter pre-emphasis; receiver adaptive equalization)
Configuration Schemes — Passive serial, fast passive parallel, JTAG, Altera enhanced configuration
RoHS 상태 — Lead-free / RoHS compliant (per Altera product family documentation)

데이터시트 & 자료

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