EP1SGX25FF1020 vs EP1SGX25FF1020C5L 对比

详细并排对比 EP1SGX25FF1020 出自 Altera 和 EP1SGX25FF1020C5L 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1SGX25FF1020 EP1SGX25FF1020C5L
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $295.00 $105.00
Family Stratix GX Stratix GX
Logic Elements (LE) 25,660 —
Configurable Logic Blocks (CLB) 2,566 —
Embedded Memory (bits) 1,944,576 —
Process Technology 130 nm CMOS 130 nm CMOS
Logic Cells (per FPGAkey) 25,660 —
Combinatorial Delay (Tpd) 7.49 ns (per Microchip USA datasheet summary) —
Operating Frequency (max) [DATA_NEEDED: max internal operating frequency] —
封装 1020-ball FCBGA (PBGA, 1.00 mm pitch) —
Pin/Package Count 1020 —
安装类型 Surface Mount (BGA) Surface Mount
工作温度 -40C to +85C (industrial variant) / 0C to +85C (commercial variant) [DATA_NEEDED: operating temperature range]
电源电压 [DATA_NEEDED: core VCC voltage] —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance]
Serial Transceivers Embedded SERDES (multi-gigabit, protocol-dependent) —
DSP Blocks Embedded dedicated multipliers [DATA_NEEDED: DSP block count]
PLL / Clock Management Embedded PLLs —
Configuration Method SRAM-based, configuration via JTAG / passive serial / fast passive parallel —
Logic Elements — 25,660 cells
Package Type — FC-FBGA (Flip-Chip Fine-pitch Ball Grid Array)
引脚数量 — 1020 balls
Core Voltage — 1.5 V
Speed Grade — C5 (slowest tier)
Maximum Transceiver Data Rate — 3.125 Gbps
Maximum Operating Frequency — 5000 MHz (internal reference)
Memory Architecture — TriMatrix (M512/M4K/M-RAM blocks)
I/O Standards Supported — LVDS, LVTTL, LVCMOS, HSTL, SSTL
Configuration Scheme — Active serial (EPCS), passive serial, JTAG

数据手册与资源

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