EP1SGX40FF1020C5 vs EP1SGX40DF1020C5ES 对比
详细并排对比 EP1SGX40FF1020C5 出自 Intel 和 EP1SGX40DF1020C5ES 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1SGX40FF1020C5 | EP1SGX40DF1020C5ES |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $1,245.00 | $0.00 |
| Family | Stratix GX | — |
| Logic Elements | 41,250 | — |
| Configurable Logic Blocks (CLBs) | 4,125 | — |
| Total RAM Bits | 3,423,744 bits | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Transceiver Channels | 20 (up to 3.125 Gbps) | — |
| Core Voltage | 1.5 V (1.425 V to 1.575 V) | — |
| 工作温度 | 0C to +85C (commercial, -C5 speed grade) | 0 C to 85 C |
| 封装 | 1020-ball FCBGA (FF), 1.00 mm pitch, 33 x 33 mm | — |
| Seated Height | 3.50 mm | — |
| Process Technology | CMOS, 0.13 um | 130 nm |
| Maximum User I/O | [DATA_NEEDED: max user I/O count] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| PLLs | [DATA_NEEDED: PLL count] | — |
| 安装类型 | Surface Mount | — |
| MSL 等级 | [DATA_NEEDED: MSL rating] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | unknown |
| Product Type | — | Field-Programmable Gate Array (FPGA) |
| Logic Family | — | Stratix GX |
| Logic Technology | — | CMOS |
| Logic Cells | — | 41,250 cells |
| Logic Array Blocks | — | 4,125 LABs |
| Configurable I/O Connections | — | 624 input and 624 output connections |
| 电源电压 | — | 1.5 V |
| Reported Maximum Frequency | — | 5,000 MHz |
| Reported Maximum CLB Combinatorial Delay | — | 7.49 ns |
| Alternative Listed Maximum Clock Frequency | — | 6 MHz |
| Terminal Count | — | 1,020 pins |
| Package Type | — | FC-FBGA-1020 |
| Package Dimensions | — | 33 mm x 33 mm |
| Ball Pitch | — | 1 mm |
| Mounting Configuration | — | Surface-mount ball grid array |
| Terminal Form | — | Ball |
| Package Code | — | BGA |
| Configuration Method | — | [DATA_NEEDED: configuration method] |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |