EP20K1000EBC652-2X vs EP20K100EBC652-2X 对比

详细并排对比 EP20K1000EBC652-2X 出自 Altera 和 EP20K100EBC652-2X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K1000EBC652-2X EP20K100EBC652-2X
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $99.00 $85.00
Family APEX-20KE APEX 20KE
Device Logic Elements 38,400 —
Typical Gates 1,000,000 system gates 100,000
Embedded Memory Bits 327,680 bits —
User I/O Pins 488 —
Maximum User I/O 488 —
Propagation Delay 1.6 ns —
Internal Maximum Frequency 350 MHz —
Logic Blocks / Macros 2,560 macros —
PLLs 4 —
Core Voltage 1.8 V —
Process Technology 0.22 µm (some sources 0.15 µm) all-layer copper-metal CMOS 0.18 µm CMOS, SRAM-based
封装 652-pin FCBGA / PBGA (45 x 45 mm, 1.27 mm pitch) 652-ball BGA (EBC652)
安装类型 Surface Mount Surface Mount
工作温度 0 °C to +85 °C (commercial) 0C to +85C (commercial)
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Altera configuration —
RoHS 状态 Compliant [DATA_NEEDED: RoHS status]
Maximum System Gates — 263,000
Logic Elements — 4,160
Embedded System Blocks (ESBs) — 26
Maximum RAM Bits — 53,248
Maximum User I/O Pins — 246
Supply Voltage - Core — 1.8 V
Supply Voltage - I/O — 1.8 V / 2.5 V / 3.3 V
Speed Grade — -2 (faster commercial)
Configuration Method — Passive Serial / Passive Parallel / JTAG (EPC)
Clock Resources — Up to 4 DLLs, multiple global clocks

数据手册与资源

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