EP20K100CQ240C7 vs EP20K100QC240-1 对比

详细并排对比 EP20K100CQ240C7 出自 Altera 和 EP20K100QC240-1 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K100CQ240C7 EP20K100QC240-1
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $92.00 $98.00
Family APEX-20K APEX 20K
Device Type FPGA (Field Programmable Gate Array) FPGA (Field-Programmable Gate Array)
System Gates 100,000 —
Logic Elements 53,248 —
Embedded Memory Bits 4,160 —
Maximum User I/O Pins 189 —
Package Type 240-BFQFP —
Speed Grade C7 -1
工作温度 0C to +85C (commercial) 0 °C to +85 °C (Commercial)
Supply Voltage - Core [DATA_NEEDED: core voltage] —
I/O Standards Supported LVTTL, LVCMOS, PCI, GTL (per family datasheet) —
Number of PLLs 4 (per APEX-20K family datasheet) —
Embedded System Blocks (ESBs) Yes (per APEX-20K family) —
安装类型 Surface Mount Surface Mount
RoHS 状态 unknown —
Lead-Free unknown —
MSL 等级 [DATA_NEEDED: MSL rating] —
Programming Tool Altera Quartus / MAX+PLUS II (per family) —
Logic Elements (LEs) — 4,160
Typical Gates — 100,000
Maximum User I/O — 189
Embedded RAM Bits — 53,248
Process Technology — 0.22 µm CMOS
Core Supply Voltage — 2.5 V
Maximum Internal Frequency — 250 MHz
封装 — 240-pin PQFP (QFP-240)
Package Code — S-PQFP-G240
Terminal Form — Gull Wing
Propagation Delay — 1.6 ns (per datasheet, typical)
JTAG Support — IEEE 1149.1 Boundary Scan
Programming — In-system (SRAM-based) via Quartus / MAX+PLUS II

数据手册与资源

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