EP20K100QC240-2 vs EP20K100QC240-3 对比

详细并排对比 EP20K100QC240-2 出自 Altera 和 EP20K100QC240-3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP20K100QC240-3 EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 ✓ 量产中

规格对比

参数 EP20K100QC240-2 EP20K100QC240-3
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 有效
库存状态 有库存 有库存
单价(USD) $0.00 $24.50
Series APEX-20K —
Device Type Field Programmable Gate Array (FPGA) —
Number of Logic Elements/Cells 4160 —
Number of LABs/CLBs 416 —
Number of User I/Os 189 —
Total RAM Bits 53248 53248 bits
Typical Gate Count 100000 263000 gates
Maximum System Gates 263000 —
工作电源电压 2.375 V to 2.625 V (2.5 V nominal) —
工作温度范围 0°C to 85°C (TJ) 0 °C to +85 °C (commercial)
Maximum Internal Frequency 200 MHz —
Propagation Delay 3 ns [DATA_NEEDED: propagation delay timing table]
封装 / 外壳 240-BFQFP (PQFP-240) —
Number of Pins / Terminals 240 —
Terminal Pitch 0.5 mm —
安装类型 Surface Mount Surface Mount
Technology / Process CMOS, 0.22 µm —
Speed Grade -2 -3
RoHS 状态 Unknown —
Manufacturer — Altera
FPGA Family — APEX-20K
Number of Logic Elements — 4160 cells
Number of User I/O — 189
Core Supply Voltage — 2.5 V
最大时钟频率 — 167 MHz (family rating)
Technology Process — 0.22 um
Package Type — 240-BFQFP
引脚数 — 240
Supported I/O Standards — [DATA_NEEDED: supported I/O standards]
Configuration / JTAG Interface — [DATA_NEEDED: configuration and JTAG interface details]
RoHS Compliance — [DATA_NEEDED: RoHS compliance for non-N version]

数据手册与资源

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