EP20K100QC240-3N vs EP20K100QC240-3 对比

详细并排对比 EP20K100QC240-3N 出自 Altera 和 EP20K100QC240-3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP20K100QC240-3 EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 ✓ 量产中

规格对比

参数 EP20K100QC240-3N EP20K100QC240-3
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $0.00 $24.50
Device Type FPGA —
Family APEX-20K —
Gate Count 100000 gates —
Logic Cells 4160 cells —
User I/O 189 I/O —
Distributed Memory 53248 bits —
Macrocells 416 macrocells —
电源电压 2.375 V to 2.625 V —
Nominal Supply 2.5 V —
Maximum Frequency 167 MHz —
工作温度 0 C to 85 C —
封装 240-BFQFP —
引脚数量 240 pins —
安装类型 Surface Mount Surface Mount
Fabrication Process 0.15 um all-layer copper-metal process —
Package Pitch 1.27 mm —
Package Dimensions 45 mm x 45 mm —
RoHS 状态 unknown —
AEC-Q100 not_qualified —
Manufacturer — Altera
FPGA Family — APEX-20K
Number of Logic Elements — 4160 cells
Total RAM Bits — 53248 bits
Number of User I/O — 189
Typical Gate Count — 263000 gates
Core Supply Voltage — 2.5 V
最大时钟频率 — 167 MHz (family rating)
Speed Grade — -3
Technology Process — 0.22 um
Package Type — 240-BFQFP
引脚数 — 240
工作温度范围 — 0 °C to +85 °C (commercial)
Propagation Delay — [DATA_NEEDED: propagation delay timing table]
Supported I/O Standards — [DATA_NEEDED: supported I/O standards]
Configuration / JTAG Interface — [DATA_NEEDED: configuration and JTAG interface details]
RoHS Compliance — [DATA_NEEDED: RoHS compliance for non-N version]

数据手册与资源

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