EP20K200EBC652-3 vs EP20K1000EBC652-2X 对比

详细并排对比 EP20K200EBC652-3 出自 Intel 和 EP20K1000EBC652-2X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K200EBC652-3 EP20K1000EBC652-2X
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $210.00 $99.00
Family APEX-20KE APEX-20KE
Logic Elements (LEs) 8,320 —
Logic Array Blocks (LABs) 832 —
Total RAM Bits 106,496 —
Maximum User I/O Pins 376 —
Embedded System Blocks (ESBs) Yes (dual-port RAM / ROM / CAM) —
PLLs 4 4
封装 652-ball FineLine BGA (top-side, 1.27 mm pitch) 652-pin FCBGA / PBGA (45 x 45 mm, 1.27 mm pitch)
安装类型 Surface Mount Surface Mount
工作温度 0C to +85C (EBC - Enhanced Commercial) 0 °C to +85 °C (commercial)
Speed Grade -3 —
Configuration Mode JTAG / PS / Passive-serial / Passive-parallel —
Process Node [DATA_NEEDED: process node] —
Core Voltage [DATA_NEEDED: core voltage] 1.8 V
RoHS 状态 Not RoHS (non-lead-free variant) Compliant
生命周期状态 Obsolete - last time-buy period closed —
Device Logic Elements — 38,400
Typical Gates — 1,000,000 system gates
Embedded Memory Bits — 327,680 bits
User I/O Pins — 488
Maximum User I/O — 488
Propagation Delay — 1.6 ns
Internal Maximum Frequency — 350 MHz
Logic Blocks / Macros — 2,560 macros
Process Technology — 0.22 µm (some sources 0.15 µm) all-layer copper-metal CMOS
Configuration Interface — JTAG (IEEE 1149.1), Passive Serial, Altera configuration

数据手册与资源

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