EP20K200EQC208-3 vs EP20K200EBC652-3N 对比
详细并排对比 EP20K200EQC208-3 出自 Intel 和 EP20K200EBC652-3N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K200EQC208-3 | EP20K200EBC652-3N |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $65.00 | $220.00 |
| Family | APEX 20KE | — |
| Series | APEX 20K (enhanced "E" variant) | APEX 20KE (APEX-20KE®) |
| Product Type | FPGA (Field Programmable Gate Array), SRAM-based, in-system programmable | — |
| System Gates (typical) | 200,000 | — |
| Logic Elements (LEs) | 8,320 | — |
| Embedded RAM Bits | 106,496 | — |
| Maximum User I/O | 136 | — |
| Speed Grade | -3 | -3 (slowest in APEX 20KE family) |
| Core Supply Voltage (VCCINT) | 2.5 V (typical, APEX 20KE generation) | — |
| I/O Supply Voltage (VCCIO) | MultiVolt, 1.8 V / 2.5 V / 3.3 V / 5 V compatible | — |
| 封装 | 208-BFQFP / PQFP208 (Plastic Quad Flat Pack, gull-wing) | 652-ball BGA |
| Terminal Pitch | 0.5 mm | — |
| 安装类型 | Surface Mount | Surface Mount |
| Technology | CMOS, SRAM configuration cell | — |
| Configuration Mode | Fast Passive Parallel (FPP), Passive Serial (PS), JTAG (IEEE 1149.1) | — |
| Embedded Array Blocks (EABs) | Yes (dual-port RAM/ROM, up to 16-bit wide) | — |
| MultiVolt I/O Support | Yes | — |
| LVDS Support | True-LVDS (enhanced "E" variant feature) | — |
| 湿敏等级（MSL） | 3 (168 Hours) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Operating Temperature (Commercial) | 0 °C to 85 °C | — |
| Device Family | — | EP20K200 |
| System Gates | — | 200,000 |
| Logic Elements / Cells | — | 8,320 |
| Logic Array Blocks (LABs) | — | 832 |
| Macrocells | — | 832 |
| Embedded RAM | — | 106,496 bits |
| User I/Os (DigiKey listing) | — | 376 |
| User I/Os (digchip listing) | — | 277 |
| Propagation Delay | — | 2.33 ns |
| Internal Frequency (max) | — | 189 MHz |
| Process Technology | — | 0.22 µm CMOS |
| Core Supply Voltage | — | 1.71 V to 1.89 V (nominal 1.8 V) |
| I/O Supply (LVDS-capable) | — | LVDS, 2.5 V referenced (per source variant) |
| Operating Temperature (TJ) | — | 0 °C to 85 °C (commercial) |
| Configuration | — | JTAG (IEEE 1149.1), Passive Serial |