EP20K30EFC144-3N vs EP20K30EFC144-2X 对比

详细并排对比 EP20K30EFC144-3N 出自 Altera 和 EP20K30EFC144-2X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP20K30EFC144-2X EP20K30EFC144-2X - 30K Gate APEX 20K FPGA | Altera

EP20K30EFC144-2X - 30K Gate APEX 20K FPGA | Altera

EP20K30EFC144-2X Obsolete

规格对比

参数 EP20K30EFC144-3N EP20K30EFC144-2X
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $64.00 $58.50
Family APEX 20K —
Typical Gates 30,000 30,000 gates
Logic Elements (Cells) 1,200 —
Embedded Memory (RAM bits) 24,576 —
User I/Os 408 —
引脚数量 144 —
Package Type 144-LBGA (FineLine BGA) —
Speed Grade -3 -2X
Internal Frequency (max) 160 MHz —
Propagation Delay (typical) 1.68 ns —
Process Technology 0.22 µm CMOS 0.22 um
Core Supply Voltage 1.8 V 1.8 V
工作温度 0 °C to 85 °C (commercial) —
Architecture MultiCore (LUT + product-term + ESB) —
Configuration Memory SRAM (volatile, requires boot PROM) —
安装类型 Surface Mount Surface Mount
RoHS 状态 unknown unknown
Device Family — Altera APEX 20K
Device Type — Loadable programmable logic device (FPGA/CPLD hybrid)
Number of Logic Elements / Cells — 1,200 cells (third-party parametric listing)
Number of Macrocells — 192
Number of User I/O — 93
Number of Terminals — 144
Terminal Form — Ball
Package Code — LBGA / 144-FBGA
Package Shape — Square
工作温度范围 — [DATA_NEEDED: exact operating temperature range]
Embedded RAM Bits — [DATA_NEEDED: embedded memory size]
Supported I/O Standards — [DATA_NEEDED: supported I/O standards]
Configuration Schemes — [DATA_NEEDED: supported configuration schemes]

数据手册与资源

浏览全部产品 创建 BOM 获取报价