EP20K30EFC324-1 vs EP20K100EFC324-1N 对比

详细并排对比 EP20K30EFC324-1 出自 Altera 和 EP20K100EFC324-1N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K30EFC324-1 EP20K100EFC324-1N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $99.50 $108.00
Manufacturer Altera (now Intel) —
Series APEX-20K —
Family APEX-20KE (1.8V, LVDS) APEX-20KE
Logic Elements (typical) 30,000 (30KLE) —
Typical Gates [DATA_NEEDED: typical gate count] 100,000
Total RAM Bits 24576 —
Maximum User I/O 128 246
Core Supply Voltage (VCCINT) 1.71 V to 1.89 V —
I/O Supply Voltage [DATA_NEEDED: VCCIO range] —
封装 324-FBGA (FineLine BGA, 19x19 mm) 324-BGA (FineLine BGA)
安装类型 Surface Mount —
引脚数量 324 —
Temperature Grade Commercial (per Altera family specification) —
工作温度 0C to +85C (commercial grade per Altera family spec) 0 C to 85 C
Process Technology SRAM-based, 0.18 um 0.15 µm all-layer copper CMOS
Configuration Passive serial / passive parallel / JTAG —
Lead-Free / RoHS [DATA_NEEDED: RoHS compliance] —
Speed Grade -1 —
MSL 等级 [DATA_NEEDED: MSL moisture sensitivity level] —
PLLs Up to 4 (per APEX-20KE family) —
Device Type — FPGA (Field Programmable Gate Array)
Logic Elements (LEs) — 4160
Embedded System Blocks (ESBs) — 53248 bits
Propagation Delay — 1.6 ns
Internal Operating Frequency — 250 MHz
Core Voltage — 1.8 V
I/O Standard Support — LVDS, SSTL, HSTL, LVTTL, LVCMOS
JTAG Support — IEEE 1149.1 boundary-scan
Programming Technology — SRAM-based (volatile, requires configuration device)
MultiVolt I/O — 1.8 V core with 3.3 V / 5.0 V I/O support

数据手册与资源

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