EP20K400CF672C7N vs EP20K400CF672I7 对比

详细并排对比 EP20K400CF672C7N 出自 Altera 和 EP20K400CF672I7 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400CF672C7N EP20K400CF672I7
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $160.00 $190.50
Family APEX 20KC APEX 20KC
Maximum System Gates 1,052,000 400,000
Typical Gates 400,000 —
Logic Elements (LEs) 16,640 —
Embedded Memory 488 Kbits —
Maximum User I/O 488 —
User I/O (per catalog) 480 / 502 (per source) —
封装 672-ball FineLine BGA (FC-FBGA / BBGA) 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA)
Process Technology 0.18-micron CMOS, all-layer copper interconnect 0.15 um CMOS
Core Voltage (VCCINT) 1.8 V —
I/O Voltage (VCCIO) 3.3 V / 2.5 V banked —
Propagation Delay 2.5 ns (catalog) / 1.48 ns (some catalog) —
Maximum Frequency 375.94 MHz (internal) —
工作温度 0 C to 85 C (Commercial) -40 C to +85 C (industrial)
安装类型 Surface Mount (BGA) —
MSL 等级 3 (per JEDEC J-STD-020) —
RoHS 状态 [DATA_NEEDED: RoHS status not in provided data] —
Configuration Modes PS, PPS, JTAG —
Logic Elements — 16,640
Embedded Memory (ESB) — 212,992 bits
Maximum User I/O Pins — [DATA_NEEDED: pin count for CF672 package]
Core Supply Voltage — 1.8 V
I/O Supply Voltage — 1.8 V / 3.3 V
PLL Count — 4
Speed Grade — I7
Terminal Finish — Tin/Lead (Sn/Pb)
JESD-609 Code — e0
湿敏等级(MSL) — 3
Configuration Mode — PS / AS / JTAG (IEEE 1149.1)

数据手册与资源

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