EP20K400GC655-2N vs EP20K400GC655-1 对比
详细并排对比 EP20K400GC655-2N 出自 Altera 和 EP20K400GC655-1 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 Obsolete规格对比
| 参数 | EP20K400GC655-2N | EP20K400GC655-1 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $127.50 | $135.00 |
| Family | APEX 20KC | APEX 20K |
| Number of Logic Elements | 16640 | — |
| Number of Logic Cells | 16640 | — |
| Total System Gates | 400000 | — |
| Total RAM Bits | 212992 | 212,992 |
| Number of I/O | [DATA_NEEDED: I/O count] | — |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Voltage (VCCIO) | 2.5 V (LVDS-capable) | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Maximum Operating Frequency | 200 MHz | — |
| Propagation Delay (Tpd) | 3.1 ns | — |
| 封装 / 外壳 | 655-BCPGA (Ceramic Pin Grid Array) | — |
| Supplier Device Package | 655-CPGA, 62.48 x 62.48 mm | — |
| 工作温度 | Industrial (per Altera part-number -N suffix) | 0 °C to +85 °C (commercial) |
| 安装类型 | Through-Hole (CPGA, socket-compatible) | Through-Hole |
| LVDS Support | Yes | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Configuration Method | JTAG / Passive Serial | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | Non-compliant (contains lead in ceramic package) |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| Series | — | EP20K400 |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 3.3 V |
| Maximum Internal Frequency | — | 250 MHz |
| Propagation Delay | — | 2.5 ns |
| 封装 | — | 655-pin CPGA (Ceramic Pin Grid Array) |
| 引脚数量 | — | 655 |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |