EP20K400GI655-1X vs EP20K400GI655-2 对比

详细并排对比 EP20K400GI655-1X 出自 Altera 和 EP20K400GI655-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400GI655-1X EP20K400GI655-2
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $160.00 $175.00
Family APEX 20K —
Device EP20K400 —
Logic Elements 16640 —
Number of Terminals 655 655
User I/O Lines 502 —
Dedicated Inputs 4 6
Package Type Ceramic Pin Grid Array (CPGA) —
Package Code (JESD-30) S-CPGA-P655 —
Package Equivalence Code SPGA655,47X47 —
Package Body Material CERAMIC (metal-sealed co-fired) —
Speed Grade -1 —
Propagation Delay 2.5 ns (typical for -1 grade) 3.1 ns (typical)
Process Technology CMOS, SRAM-based configuration —
湿敏等级(MSL) 1 —
Peak Reflow Temperature 220 C —
工作温度 -40 C to +85 C (industrial) -40C to +85C (industrial)
安装类型 Through-Hole (PGA) Through-Hole / Socket
RoHS 状态 Compliant [DATA_NEEDED: RoHS status]
Manufacturer — Altera Corporation
Series — APEX 20K (EP20K400)
Device Type — Field Programmable Gate Array (FPGA)
Typical Gate Count — 400,000 gates
Logic Elements (LE) — 16,640
Maximum User I/O — 496
封装 — SPGA-655 (47 mm x 47 mm)
Nominal Supply Voltage — 2.5 V
Supply Voltage Range — 2.375 V to 2.625 V
Technology — CMOS SRAM
Moisture Sensitivity Level — 1 (per Altera family)
Configuration Method — JTAG, Passive Serial, Passive Parallel
I/O Standards Supported — LVTTL, LVCMOS, PCI, GTL+
Embedded Memory — Embedded System Blocks (ESBs)
生命周期状态 — Obsolete (legacy Altera APEX 20K family)

数据手册与资源

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