EP20K600CB652C9N vs EP20K600CB652C8N 对比
详细并排对比 EP20K600CB652C9N 出自 Intel 和 EP20K600CB652C8N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K600CB652C9N | EP20K600CB652C8N |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $128.00 | $115.00 |
| Family | APEX 20KC | APEX 20KC |
| Device Type | Loadable PLD (FPGA) | Loadable PLD / FPGA |
| Typical Gates | 600,000 | — |
| Logic Elements | 24,320 | 24,320 cells |
| Maximum User I/O | 488 | — |
| 封装 | BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) | 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch |
| Process Technology | 0.15 micron all-layer copper CMOS | 0.18 µm all-layer copper-metal |
| Core Supply Voltage | 1.8 V | 1.8 V nominal (1.71 V to 1.89 V) |
| Speed Grade | C9 (~1.48 ns propagation delay) | C8 |
| Architecture | MultiCore LUT + embedded system memory (ESB) | MultiCore LUT + Embedded System Blocks (ESB) |
| On-chip Memory | Embedded system memory blocks (dual-port RAM, FIFO) | — |
| Configuration Interface | JTAG (IEEE 1149.1) and serial/PROM configuration | — |
| 工作温度 | 0 C to 85 C (commercial) | 0 °C to 85 °C (commercial) |
| 安装类型 | Surface Mount (BGA) | Surface Mount (BGA) |
| Pin/Pin Compatibility | Pin-compatible with APEX 20KE devices of same package | — |
| Toolchain | Altera/Intel Quartus II (legacy APEX support) | — |
| RoHS 状态 | [DATA_NEEDED: rohs status] | unknown |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| System Gates | — | 600,000 |
| Embedded Memory | — | 311,296 bits |
| User I/O Pins | — | 488 |
| Dedicated Inputs | — | 4 |
| Outputs | — | 480 |
| Propagation Delay (typ.) | — | 1.48 ns |
| Pin-to-Pin Timing | — | 1.78 ns |
| Internal Frequency (typ.) | — | 301.21 MHz |
| Pin-Compatible With | — | APEX 20KE family |