EP20K600CF672C7ES vs EP20K600CF672C6 对比

详细并排对比 EP20K600CF672C7ES 出自 Altera 和 EP20K600CF672C6 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP20K600CF672C7ES EP20K600CF672C7ES - APEX 20KC FPGA 600K Gates 672-FBGA | Altera

EP20K600CF672C7ES - APEX 20KC FPGA 600K Gates 672-FBGA | Altera

EP20K600CF672C7ES ⚠ 最后一次采购

规格对比

参数 EP20K600CF672C7ES EP20K600CF672C6
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $360.00 $480.00
Series APEX 20KC —
Family APEX 20K APEX 20KC
Logic Elements / Cells 24320 —
System Gates 600000 —
Maximum User I/O 504 —
Maximum Input Lines 508 —
Number of Macrocells 504 —
Maximum Operating Frequency 375.94 MHz (per FPGAkey listing) —
Propagation Delay 1.6 ns —
Internal Reference Clock 1666.6 MHz —
Process Technology 0.15 µm CMOS 0.18 µm CMOS, 6 metal layers
Core Supply Voltage (VCCINT) 1.8 V —
Package Type FC-FBGA —
Pin / Ball Count 672 —
Grade Suffix ES (engineering sample / extended screening) —
工作温度 [DATA_NEEDED: operating temperature grade] 0 °C to +85 °C (commercial)
安装类型 Surface Mount (BGA) —
MSL 等级 [DATA_NEEDED: MSL rating] —
RoHS 状态 [DATA_NEEDED: RoHS compliance] Non-RoHS (legacy process)
Configuration Memory SRAM-based (volatile) —
Typical Gate Count — 600,000 gates
Logic Elements (LEs) — 24,320
Embedded System Blocks (ESBs) — 160 (each 2,048 bits)
Maximum Embedded RAM — 311,296 bits (311 kbit)
Maximum User I/O Pins — 508
封装 — 672-ball FineLine BGA (CF672)
Package Body Size — 27 mm × 27 mm
Speed Grade — -6 (C6)
Core Voltage — 1.8 V
I/O Standards Supported — LVCMOS, LVTTL, HSTL, SSTL, GTL+
Embedded PLLs — 4
Configuration Method — SRAM-based, JTAG, EPC16/EPC2

数据手册与资源

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