EP20K600CF672I-8ES vs EP20K600CF672I8 对比

详细并排对比 EP20K600CF672I-8ES 出自 Altera 和 EP20K600CF672I8 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K600CF672I-8ES EP20K600CF672I8
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $119.00 $195.00
Family APEX 20KC APEX 20KC
Logic Elements 24,320 —
Typical Gates 600,000 (ASIC-equivalent) —
Embedded Memory Bits 311,296 —
Maximum User I/O Pins 508 —
Embedded PLLs 4 —
Core Voltage 1.8 V —
I/O Standards Supported LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ —
Process Technology 0.18 micron CMOS SRAM 0.15 µm all-layer copper
Speed Grade -8 (slower) —
工作温度 -40C to +100C (Industrial) 0 °C to +85 °C (Industrial)
封装 672-ball BGA (FineLine BGA, 1.27 mm pitch) —
Configuration Modes Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous, JTAG —
In-System Programmability Yes (ISP via EPC16, EPC8, EPC4, EPC2, EPC1) —
RoHS 状态 Non-compliant (legacy Altera leaded BGA process) Compliant per legacy product records
MSL 等级 [DATA_NEEDED: moisture sensitivity level] —
Device Type — SPLD / FPGA
Logic Elements / Cells — 24,320
Macros (Logic Cells) — 2432
Typical Gate Count — 600,000 gates
Embedded Memory — 311,296 bits
User I/Os — 488 to 508
引脚数 — 652 (functional) / 672 (BGA balls)
Propagation Delay (typical) — 1.48 ns
Internal Frequency (max) — [DATA_NEEDED: max internal frequency in MHz]
Core Supply Voltage — 1.8 V
Package Type — 672-ball BGA, 45 x 45 mm, 1.27 mm pitch
安装类型 — Surface Mount
Configuration Interface — JTAG / Passive Serial
Design Tool — Quartus II (legacy MAX+PLUS II)

数据手册与资源

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