EP2A15B652C7 vs EP2A25B652C7 对比

详细并排对比 EP2A15B652C7 出自 Intel 和 EP2A25B652C7 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A15B652C7 EP2A25B652C7
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $82.40 $285.00
Family APEX II APEX II
Logic Elements 30000 (approx) Approximately 25,000 LE
Typical Gates 1.5 million —
Maximum User I/O Pins [DATA_NEEDED: exact user I/O count] 488
Process Technology 0.18 micron CMOS —
Embedded System Blocks (ESB) Yes - configurable as RAM/ROM or product-term logic —
Supply Voltage - Core [DATA_NEEDED: VCCINT voltage] —
Supply Voltage - I/O [DATA_NEEDED: VCCIO voltage] —
Configuration Method SRAM-based, requires external configuration memory JTAG / Passive Serial / Active Serial
Speed Grade -7 -7
工作温度 0C to +85C (commercial, suffix C7) Commercial 0C to +85C
封装 652-ball BGA 652-ball FineLine BGA
安装类型 Surface Mount —
Hot Socketing Support Yes (MultiCore hot-socketing) —
RoHS 状态 [DATA_NEEDED: RoHS status - legacy APEX II family] [DATA_NEEDED: RoHS status]
Design Tool Quartus II (legacy) —
Embedded System Blocks (ESBs) — [DATA_NEEDED: ESB count]
Core Voltage — 1.5 V
I/O Bank Voltage — 1.5 V / 1.8 V / 2.5 V / 3.3 V
RAM Bits (approx.) — 40,960
PLLs — 4
Supported I/O Standards — LVTTL, LVCMOS, SSTL, LVDS
Boundary Scan — IEEE 1149.1 compliant
Design Software — Quartus II

数据手册与资源

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