EP2A15B724C7 vs EP2A40B724C7 对比

详细并排对比 EP2A15B724C7 出自 Altera 和 EP2A40B724C7 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A15B724C7 EP2A40B724C7
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $125.00 $650.00
Family APEX II APEX II
Manufacturer Altera (acquired by Intel) —
System Gates 600,000 —
Logic Elements / Cells 16,640 38,400
Total RAM Bits 425,984 —
Number of I/O 492 —
Core Voltage 1.425 V to 1.575 V —
工作温度 0 C to 85 C (TJ) 0 °C to +85 °C (commercial)
封装 724-BBGA, FCBGA (35 mm x 35 mm) 724-ball FCBGA (FineLine BGA), 35 mm x 35 mm
安装类型 Surface Mount (BGA) Surface Mount (BGA)
Speed Grade C7 (per part suffix) —
Maximum Internal Frequency 500 MHz 562 MHz
Process Technology 0.15 um all-layer copper 0.15 µm CMOS, up to 8 metal layers, all-layer copper
LVDS Support True-LVDS up to 1 Gbps —
Interface Standards True-LVDS, LVPECL, PCML, HyperTransport —
Configuration Modes Passive Serial, Passive Parallel, JTAG —
RoHS 状态 unknown Non-compliant (lead-bearing FCBGA)
Total System Gates — 1,500,000
Embedded RAM Bits — 655,360
Maximum User I/O — 540
Core Supply Voltage — 1.425 V to 1.575 V (typ. 1.5 V)
PLLs — 4
I/O Standards Supported — LVTTL, LVCMOS, 1.5 V/1.8 V/2.5 V/3.3 V, SSTL, HSTL, PCI, LVDS, LVPECL, PCML, HyperTransport, True-LVDS (1 Gbps)
Configuration Method — JTAG (IEEE 1149.1), Passive Serial, Passive Parallel, Active Serial via EPC configuration devices
MultiVolt I/O Support — 1.5 V, 1.8 V, 2.5 V, 3.3 V
DDR Memory Support — Yes (via ESB / I/O circuitry)
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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