EP2A15B724C9 vs EP2A15B724C 对比

详细并排对比 EP2A15B724C9 出自 Intel 和 EP2A15B724C 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A15B724C9 EP2A15B724C
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $268.50 $195.00
Series APEX II —
Family APEX II (EP2A15) APEX II
Logic Elements 16640 —
Number of Gates 600000 —
Embedded Memory (RAM bits) 425984 —
User I/O Count 492 —
Supply Voltage (Core) 1.5 V —
I/O Voltages Supported 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) —
Process Technology 0.15 µm all-layer copper (up to 8 metal layers) 0.18 micron CMOS
Maximum Internal Frequency 500 MHz —
LVDS Data Rate Up to 1 Gbps (True-LVDS) —
Interface Standards LVDS, LVPECL, PCML, HyperTransport —
Embedded Memory Type ESB - dual-port RAM / ROM / FIFO / CAM —
Clock Management On-chip PLLs —
封装 724-ball FCBGA (Fine-pitch Chip-Scale BGA) 724-Ball FCBGA (FineLine BGA)
工作温度 Commercial (0 °C to +85 °C) [DATA_NEEDED: operating temperature grade]
安装类型 Surface Mount Surface Mount (BGA)
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Logic Elements (LEs) — 16,640
Maximum User I/O Pins — 492
Embedded RAM — 425,984 bits
Maximum System Gates — Up to 1.5M gates (family-level)
Embedded System Blocks (ESBs) — Configurable as dual-port RAM / ROM / FIFO
Interconnect — MultiTrack, deterministic
I/O Standards — LVTTL, LVCMOS, LVDS, PCI, GTL+ (family-level)
PLLs — Yes (family-level, up to 4 per device)
MSL 等级 — [DATA_NEEDED: MSL rating]
Speed Grade — C (per suffix; specific speed bin [DATA_NEEDED])
JTAG / Configuration — IEEE 1149.1 JTAG; passive serial / PS configuration supported (family-level)

数据手册与资源

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