EP2A25F672C7N vs EP2A25F672C9N 对比

详细并排对比 EP2A25F672C7N 出自 Altera 和 EP2A25F672C9N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A25F672C7N EP2A25F672C9N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $195.00 $195.00
Family APEX II APEX II
Logic Elements 24,320 cells —
System Gates Approximately 900,000 Approx. 900000
User I/Os 492 —
Propagation Delay (tPD) 1.69 ns —
Internal Operating Frequency Up to 500 MHz —
Core Voltage (VCCINT) 1.5 V —
Process Technology 0.15 µm all-layer copper (up to 8 metal layers) 0.15 µm all-layer copper, up to 8 metal layers
Logic Family CMOS CMOS
Package Type 672-ball FC-FBGA (FineLine BGA) —
Package Body Size 27 x 27 mm —
Ball Pitch 1.0 mm —
工作温度 0 °C to 85 °C (commercial) 0 °C to +85 °C (commercial, C9 grade)
High-Speed I/O Support True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps —
Programmable Logic Type Loadable PLD (in-system programmable) —
Embedded Memory Embedded System Blocks (ESB) configurable as dual-port RAM/ROM Enhanced System Blocks (ESBs) for dual-port RAM
PLLs Up to 4 —
安装类型 Surface Mount Surface Mount (BGA)
RoHS 状态 [DATA_NEEDED: RoHS compliance] Compliant (per distributor listings)
Logic Elements / Cells — 24320
Maximum User I/O — 492
Operating Frequency — 236 MHz
Core Supply Voltage (VCCINT) — 1.425 V to 1.575 V (nominal 1.5 V)
封装 — 672-ball FineLine BGA (F672), 27 × 27 mm, 1.00 mm pitch
Seated Height (max) — 2.100 mm
Propagation Delay — 2.23 ns
I/O Standards Supported — LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport
LVDS Data Rate — Up to 1 Gbps (True-LVDS)
Configuration Interface — Serial / Parallel PROM, JTAG, passive parallel (enhanced)
Design Software — Quartus II (v5.1 or later)

数据手册与资源

浏览全部产品 创建 BOM 获取报价