EP2A25F672C9 vs EP2A25F672C9N 对比
详细并排对比 EP2A25F672C9 出自 Altera 和 EP2A25F672C9N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2A25F672C9 | EP2A25F672C9N |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $700.00 | $195.00 |
| Family | APEX II | APEX II |
| Logic Elements (LE) | Approximately 25,000 | — |
| Macro Cells | 2432 | — |
| User I/O | 492 | — |
| 封装 | 672-ball FCBGA (FineLine BGA) | 672-ball FineLine BGA (F672), 27 × 27 mm, 1.00 mm pitch |
| Package Dimensions | 27 mm x 27 mm | — |
| Ball Pitch | 1.0 mm | — |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.15 µm all-layer copper, up to 8 metal layers |
| Logic Family | CMOS | CMOS |
| Propagation Delay | 1.69 ns | 2.23 ns |
| 工作温度 | 0°C to 85°C (Commercial) | 0 °C to +85 °C (commercial, C9 grade) |
| 电源电压 | [DATA_NEEDED: core VCC voltage] | — |
| I/O Standards | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) | — |
| Configuration | Passive Serial, Passive Parallel Synchronous, JTAG | — |
| Embedded Memory | ESBs for dual-port RAM, ROM, FIFO | Enhanced System Blocks (ESBs) for dual-port RAM |
| 安装类型 | Surface Mount | Surface Mount (BGA) |
| RoHS 状态 | [DATA_NEEDED] | Compliant (per distributor listings) |
| Logic Elements / Cells | — | 24320 |
| System Gates | — | Approx. 900000 |
| Maximum User I/O | — | 492 |
| Operating Frequency | — | 236 MHz |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Seated Height (max) | — | 2.100 mm |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport |
| LVDS Data Rate | — | Up to 1 Gbps (True-LVDS) |
| Configuration Interface | — | Serial / Parallel PROM, JTAG, passive parallel (enhanced) |
| Design Software | — | Quartus II (v5.1 or later) |