EP2A25F672I-9 vs EP2A25F672C8 对比

详细并排对比 EP2A25F672I-9 出自 Intel 和 EP2A25F672C8 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A25F672I-9 EP2A25F672C8
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $195.00 $951.18
Family APEX II APEX II (EP2A25)
Logic Elements (typical) 25,000 —
Maximum System Gates [DATA_NEEDED: maximum system gates] 40,960
Embedded System Blocks (ESB) Memory 1,125 Kbits —
Maximum User I/O Pins [DATA_NEEDED: maximum user I/O pins] —
Number of PLLs 4 —
Process Technology 0.18 µm CMOS 0.15 microm CMOS, 8-layer copper interconnect
Core Voltage 1.5 V / 1.8 V (speed-grade dependent) —
Operating Temperature Grade Industrial (-40 °C to +100 °C junction) —
Speed Grade -9 C8
封装 672-pin FCBGA (FineLine BGA) 672-FBGA (FineLine BGA, 27x27 mm, 1.0 mm pitch)
安装类型 Surface Mount (BGA) Surface Mount
湿敏等级(MSL) 3 (per Vyrian listing) —
Peak Reflow Temperature 220 °C (per Vyrian listing) —
Configuration Method JTAG / serial configuration EPROM —
Supported I/O Standards LVTTL, LVCMOS, LVDS, PCI —
RoHS 状态 [DATA_NEEDED: RoHS status] Non-compliant (legacy product)
Legacy Status Obsolete - consult Altera / Intel FPGA archive for documentation —
Logic Elements — 25,000 (typical gates)
Macrocells / Embedded Logic — 2,432 macros
User I/O Count — 492
Propagation Delay (tpd) — 1.69 ns
工作温度 — 0 C to 85 C (commercial)
I/O Standards Supported — LVTTL, LVCMOS, PCI-X, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL
LVDS Data Rate — 1 Gbps
PLL Count — 4
Embedded Memory — ESB blocks (dual-port RAM, FIFO, CAM, ROM)
I/O Banks — 16

数据手册与资源

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