EP2A40B724C7 vs EP2A40B724C9 对比
详细并排对比 EP2A40B724C7 出自 Intel 和 EP2A40B724C9 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2A40B724C7 | EP2A40B724C9 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $650.00 | $395.38 |
| Family | APEX II | — |
| Logic Elements / Cells | 38,400 | — |
| Total System Gates | 1,500,000 | — |
| Embedded RAM Bits | 655,360 | 655,360 (approximately 655 Kbits / 80 Kbytes) |
| Maximum User I/O | 540 | — |
| Core Supply Voltage | 1.425 V to 1.575 V (typ. 1.5 V) | — |
| Process Technology | 0.15 µm CMOS, up to 8 metal layers, all-layer copper | — |
| Maximum Internal Frequency | 562 MHz | — |
| PLLs | 4 | — |
| 封装 | 724-ball FCBGA (FineLine BGA), 35 mm x 35 mm | — |
| 工作温度 | 0 °C to +85 °C (commercial) | 0C to +85C |
| I/O Standards Supported | LVTTL, LVCMOS, 1.5 V/1.8 V/2.5 V/3.3 V, SSTL, HSTL, PCI, LVDS, LVPECL, PCML, HyperTransport, True-LVDS (1 Gbps) | — |
| Configuration Method | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel, Active Serial via EPC configuration devices | — |
| MultiVolt I/O Support | 1.5 V, 1.8 V, 2.5 V, 3.3 V | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| DDR Memory Support | Yes (via ESB / I/O circuitry) | — |
| RoHS 状态 | Non-compliant (lead-bearing FCBGA) | [DATA_NEEDED: RoHS status] |
| MSL 等级 | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| 安装类型 | Surface Mount (BGA) | Surface Mount |
| Series | — | APEX II |
| Logic Elements (LE) | — | 38,400 |
| Number of User I/O | — | 540 |
| 工作电源电压 | — | 1.425 V to 1.575 V (core) |
| 封装 / 外壳 | — | 724-BBGA, FCBGA (Flip-Chip BGA) |
| Supplier Device Package | — | 724-BGA (35x35 mm) |
| Shipping Medium | — | Tray |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Architecture | — | LUT-based with embedded memory blocks |
| Typical Core Power | — | [DATA_NEEDED: ICCDAT typical] |