EP2A40F1020C9ES vs EP2A40F1020C8N 对比

详细并排对比 EP2A40F1020C9ES 出自 Altera 和 EP2A40F1020C8N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A40F1020C9ES EP2A40F1020C8N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $98.00 $0.00
Family APEX II —
System Gates 1.5 M —
Logic Cells / Elements 38,400 —
Maximum Internal Clock Frequency 366 MHz —
Process Technology 0.15 µm CMOS —
Core Supply Voltage 1.5 V —
封装 1020-pin FC-FBGA —
Package Type Flip-Chip Fine-Pitch Ball Grid Array FC-FBGA, BGA-1020
安装类型 Surface Mount Surface Mount
Embedded Memory Embedded System Blocks (ESBs) - RAM/ROM —
I/O Standards LVDS and other high-speed standards (per family datasheet) —
RAM Support Synchronous and asynchronous —
工作温度 [DATA_NEEDED: operating temperature grade] 0 °C to 85 °C
RoHS 状态 [DATA_NEEDED: RoHS status] unknown
Lead-Free [DATA_NEEDED: lead-free status] —
Product Type — Field-Programmable Gate Array (FPGA)
Device Family — APEX II
Logic Technology — CMOS
Logic Gates — 1.5 million
Logic Cells — 38,400
Nominal Supply Voltage — 1.5 V
Supply Voltage Range — 1.425 V to 1.575 V
User I/Os — 735
Package Terminal Count — 1,020 pins
Package Body Size — 33 mm x 33 mm
Ball Pitch — 1 mm
Reported Operating Frequency — 376 MHz
Alternative Reported Frequency — 562 MHz
Reported Propagation Delay — 1.78 ns
Alternative Reported Propagation Delay — 1.55 ns
Fabrication Process — 0.15 µm
Maximum Reported Metal Layers — 8 layers
Terminal Form — Ball
REACH Status — unknown
AEC-Q100 Qualification — unknown

数据手册与资源

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