EP2A40F672C8 vs EP2A40F672C6N 对比

详细并排对比 EP2A40F672C8 出自 Intel 和 EP2A40F672C6N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A40F672C8 EP2A40F672C6N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $68.00 $165.00
Family APEX II APEX II
Logic Family CMOS —
Typical Logic Elements (LEs) 40,000 —
Embedded Memory Up to 1.5 Mbits —
User I/Os 492 pins —
引脚数 672 —
Package Type FineLine BGA, 27 x 27 mm, 1.0 mm pitch —
Process Technology 0.15-micron all-layer copper, up to 8 metal layers SRAM-based, 0.18 um (per family datasheet)
Propagation Delay (speed grade C8) 1.55 ns —
工作温度 0 C to 85 C (commercial) Commercial (0C to +85C)
Phase-Locked Loops (PLLs) 4 —
LVDS Signaling Support Up to 1 Gbps —
Multipliers Embedded multiplier blocks —
I/O Standards LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS —
安装类型 Surface Mount (BGA) Surface Mount
Logic Elements — 40,000
Maximum System Gates — 1,125,000
Embedded RAM Bits — 442,368
Embedded System Blocks (ESBs) — 160
Maximum User I/O Pins — [DATA_NEEDED: maximum user I/O count]
Core Voltage — 1.5 V
I/O Standards Supported — LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V
封装 — 672-ball FineLine BGA
Speed Grade — C6 (per part number suffix)
Configuration Methods — Passive Serial, Passive Parallel, JTAG
RoHS 状态 — [DATA_NEEDED: RoHS compliance status]
PLL Count — [DATA_NEEDED: PLL count]

数据手册与资源

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