EP2A40F672C9 vs EP2A40F672C6 对比
详细并排对比 EP2A40F672C9 出自 Altera 和 EP2A40F672C6 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2A40F672C9 | EP2A40F672C6 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $62.00 | $105.00 |
| Family | APEX II | APEX II |
| Device Family | APEX II PLD | — |
| Logic Elements / Cells | 38,400 | — |
| System Gates | 1.5 M | — |
| Macros | 2,560 | — |
| User I/Os | 492 | — |
| 引脚数 | 672 | — |
| 封装 | 672-BBGA, FC-FBGA (FineLine) | 672-ball FineLine BGA (FBGA-672) |
| Package Size | 27 mm × 27 mm, 1 mm ball pitch | — |
| Core Voltage | 1.5 V | — |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.18-micron CMOS |
| Logic Family | CMOS | — |
| Propagation Delay | 1.55 ns | — |
| Internal Speed Grade | 366 MHz | — |
| 工作温度 | 0 °C to 85 °C (commercial) | Commercial (0C to +85C) |
| I/O Standards Supported | True-LVDS, LVPECL, PCML, HyperTransport | — |
| 安装类型 | Surface Mount | Surface Mount (BGA) |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device | — | EP2A40 |
| Logic Elements (typical) | — | 40,000 |
| Maximum System Gates | — | [DATA_NEEDED: maximum system gates] |
| Embedded System Blocks (ESBs) | — | [DATA_NEEDED: ESB count] |
| Maximum User I/O Pins | — | [DATA_NEEDED: max user I/O count] |
| Speed Grade | — | C6 (commercial) |
| Configuration Memory | — | SRAM-based |
| JTAG Support | — | Yes (IEEE 1149.1) |
| PLL Support | — | Yes |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Lifecycle | — | Obsolete / EOL (per Intel/Altera product discontinuation notice) |