EP2A70B724C7N vs EP2A70B724C8N 对比
详细并排对比 EP2A70B724C7N 出自 Altera 和 EP2A70B724C8N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2A70B724C7N | EP2A70B724C8N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $188.00 | $240.00 |
| Family | APEX II (EP2A70) | FPGA (PLD) |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Technology | 0.15 µm CMOS | — |
| System Gates | 3,000,000 | 3,000,000 (3 M) |
| Logic Cells / Logic Elements | 67,200 | — |
| Maximum Internal Frequency | 420 MHz | — |
| Propagation Delay (typ.) | 2.17 ns | — |
| User I/O Pins | 536 | — |
| Macrocells (memory blocks reference) | 16 | — |
| Core Supply Voltage | 1.5 V nominal | 1.5 V |
| I/O Supply Voltage | MultiVolt (1.5V / 1.8V / 2.5V / 3.3V / 5V tolerant) | — |
| 工作温度 | 0 °C to +85 °C (Commercial) | — |
| 封装 | 724-pin FCBGA (Flip-Chip BGA) | — |
| Ball Pitch | 1.27 mm | — |
| Seated Height | 3.5 mm | — |
| 安装类型 | Surface Mount | Surface Mount (BGA) |
| Configuration Method | JTAG, Passive Serial (PS), Fast Passive Parallel (FPP) | — |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| Embedded Memory | Embedded System Blocks (ESBs) - dual-port RAM / ROM / CAM | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | — |
| Series | — | APEX II (EP2A70) |
| Logic Elements / Cells | — | 67,200 |
| Macrocells | — | 16 |
| Product Terms | — | 32 |
| Propagation Delay | — | 2.49 ns |
| Maximum Internal Clock Frequency | — | 281 MHz |
| Maximum Clock Frequency (fMAX) | — | 1694.91 MHz |
| Process Technology | — | 0.15 um CMOS, SRAM-based |
| Architecture | — | PLA-type / LUT-based |
| Package Type | — | FCBGA-724 (square) |
| Number of Pins / Balls | — | 724 |
| Terminal Pitch | — | 1.270 mm |
| Maximum User I/O | — | 536 |