EP2AGZ300FF35C4G vs EP2AGZ300FF35C4N 对比
详细并排对比 EP2AGZ300FF35C4G 出自 Intel 和 EP2AGZ300FF35C4N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2AGZ300FF35C4G | EP2AGZ300FF35C4N |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $2,240.00 | $1,350.00 |
| Family | Arria II GZ | — |
| Logic Elements | 300,000 | 298,000 |
| Adaptive Logic Modules (ALMs) | 119,000 | — |
| Embedded Memory | 16,624 Kbit (M9K + M144K) | — |
| Embedded 18x18 Multipliers | 736 | — |
| User I/O Pins | 554 | — |
| Transceivers | 12 channels | Multi-gigabit transceivers integrated |
| Max Transceiver Data Rate | 6.375 Gbps (C4 speed grade) | — |
| 封装 | 1152-ball FineLine BGA (FBGA-1152), 35x35 mm | — |
| 工作温度 | 0°C to +85°C (commercial C4 grade) | — |
| Speed Grade | 4 | — |
| Process Technology | 40 nm TSMC | 40 nm |
| Core Voltage | 0.85 V to 1.1 V | 0.9 V |
| PLLs | 8 (up to 4 per quadrant) | [DATA_NEEDED: PLL count] |
| Global Clock Networks | 16 | — |
| PCIe Hard IP | PCIe Gen2 x4 | — |
| Hard Memory Controller | DDR3 up to 800 MHz | — |
| Configuration | Passive Serial, Fast Passive Parallel, JTAG | — |
| RoHS 状态 | Compliant | Compliant (per Besenchips / DigiKey listing) |
| MSL 等级 | 3 (168 hours) | — |
| Series | — | Arria II GZ |
| Logic Array Blocks (LABs) | — | 11,920 |
| Embedded Memory (bits) | — | 18,854,912 (~17.9 Mbit) |
| User I/O Count | — | 554 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Package Type | — | 1152-BBGA, FCBGA (flip-chip) |
| Terminal Form | — | Ball |
| Package Code (JEDEC) | — | HBGA |
| Operating Temperature Grade | — | Commercial (C4 = 0C to +85C) |
| Configuration Memory | — | SRAM-based (volatile, requires boot device) |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks] |
| Lead-Free Status | — | Lead free (per Besenchips listing) |
| 安装类型 | — | Surface Mount |
| Maximum Operating Frequency | — | 500 MHz |