EP2C50F672C7 vs EP2C35F672C8 对比
详细并排对比 EP2C50F672C7 出自 Altera 和 EP2C35F672C8 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2C50F672C7 | EP2C35F672C8 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $184.59 | $71.85 |
| Family | Cyclone II | Cyclone II |
| Logic Elements (LE) | 50,528 | — |
| Embedded Memory Bits | 594,432 bits | — |
| Embedded Memory Blocks | 250 M4K blocks (4 Kbit each) | — |
| Embedded 18x18 Multipliers | 86 (150 per device family datasheet figure) | — |
| User I/O Pins | 450 | — |
| Phase-Locked Loops (PLL) | 4 | — |
| Global Clock Networks | 16 | — |
| Process Technology | 90 nm CMOS with low-k dielectric | 90 nm |
| Core Voltage (VCCINT) | 1.2 V | 1.15 V - 1.25 V |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V (per bank) | — |
| 封装 | 672-ball FineLine BGA (FBGA-672) | 672-BGA (FineLine BGA, 1.0 mm pitch) |
| Speed Grade | -7 | C8 (commercial, 8 ns pin-to-pin) |
| Temperature Grade | Commercial (0C to +85C junction) | — |
| Configuration Modes | Passive Serial (PS), Active Serial (AS), JTAG | Active Serial (AS), Passive Serial (PS), JTAG |
| Lead-Free / RoHS | Lead-Free / RoHS compliant per Heisener listing | — |
| Logic Elements (LEs) | — | 33,216 |
| Total RAM Bits | — | 483,840 |
| Embedded Multipliers (18x18) | — | 35 |
| User I/O Pins (max) | — | 475 |
| Number of PLLs | — | 4 |
| Operating Temperature (Commercial) | — | 0C to +85C |
| Memory Interface Support | — | DDR, DDR2, SDR SDRAM |
| I/O Standards | — | LVTTL, LVCMOS, SSTL, LVDS, RSDS, mini-LVDS, PPDS |
| 安装类型 | — | Surface Mount |
| RoHS 状态 | — | Compliant (lead-free package) |