EP2S60F1020I4 vs EP2S60F1020C4N 对比

详细并排对比 EP2S60F1020I4 出自 Altera 和 EP2S60F1020C4N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2S60F1020I4 EP2S60F1020C4N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $1,454.92 $67.00
Manufacturer Intel / Altera —
Series Stratix II Stratix II
Logic Elements (LEs) 60,440 —
Embedded Memory (bits) 2,544,192 2,544,192
Number of LABs/CLBs 3022 —
Number of CLBs 24176 —
Maximum User I/O 718 —
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Operating Voltage (Core) 1.2 V —
Process Technology 90 nm CMOS 90 nm CMOS
Temperature Grade Industrial (-40C to +100C TJ) —
Package Type 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) —
Package Dimensions 33 mm x 33 mm —
Ball Pitch 1.0 mm —
安装类型 Surface Mount Surface Mount (BGA)
Configuration Method Passive Serial / Fast Passive Parallel / JTAG —
Number of PLLs 12 —
Global Clock Networks 16 —
Embedded Multipliers (18x18) 36 —
Transceiver Count 0 (no embedded transceivers) —
Maximum Embedded Memory Bandwidth [DATA_NEEDED: memory bandwidth spec] —
RoHS 状态 Non-compliant (contains lead per legacy Altera package) EU RoHS compliant with exemption (per Arrow listing)
Family — Stratix II (EP2S60)
Logic Elements — 60,440
Adaptive Logic Modules (ALMs) — 30,220 (approx.)
Logic Array Blocks (LABs) — 3,022
Embedded Memory Blocks — M512/M4K/M-RAM TriMatrix memory
DSP Blocks (18-bit x 18-bit) — Up to 48 (24 per DSP block column pair typical)
User I/Os — 718
Maximum Core Frequency — 711.24 MHz (per Arrow listing)
Core Voltage — 1.2 V
封装 — 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA)
Operating Temperature Grade — Commercial (C4 suffix indicates commercial, speed grade 4)
Configuration Modes — Passive Serial, Fast Passive Parallel, JTAG
PLLs / Clock Networks — Yes - on-chip PLLs and global clock networks

数据手册与资源

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