EP2S60F484C3N vs EP2S60F484C5 对比
详细并排对比 EP2S60F484C3N 出自 Intel 和 EP2S60F484C5 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2S60F484C3N | EP2S60F484C5 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $1,245.75 | $491.55 |
| Family | Stratix II | Stratix II |
| Logic Elements | 60,440 | 60440 |
| Adaptive LUTs (ALUTs) | 48,352 | — |
| Embedded Memory (TriMatrix) | 2,544 Kbits (M4K + M512 + M-RAM) | — |
| Embedded DSP Blocks | 12 (48 GMACs at 450 MHz) | — |
| Maximum User I/O Pins | 334 | — |
| 封装 | 484-BGA (F484), 1.0 mm pitch | 484-pin FC-FBGA (FBGA) |
| Process Technology | 90 nm CMOS, 1.2 V core | 90 nm CMOS |
| Speed Grade | -3 (fastest commercial) | C5 (Commercial) |
| Operating Temperature (Commercial) | 0C to +85C (TJ) | — |
| Supply Voltage VCCINT | 1.2 V nominal | — |
| Configuration Modes | FPP, AS, PS, JTAG | — |
| MSL 等级 | 3 (per JEDEC J-STD-020) | 3 (168 hours) |
| RoHS 状态 | Compliant | Compliant |
| Lead-Free | Yes | — |
| Configurable Logic Blocks (CLBs) | — | 24176 |
| Logic Array Blocks (LABs) | — | 3022 |
| Embedded Memory (RAM bits) | — | 2,544,192 |
| Maximum User I/O | — | 334 |
| Package Size | — | 23 x 23 mm |
| Ball Pitch | — | 1.0 mm |
| Core Voltage (VCCINT) | — | 1.2 V |
| Maximum Internal Frequency | — | 609.76 MHz |
| 工作温度 | — | Commercial (0C to +85C) |
| 安装类型 | — | Surface Mount (BGA) |